A new approach for quality-adjusting PPI microprocessors

Measuring the price changes of “high-tech” goods can be challenging. These types of goods see rapid technological improvements, which must be valued so that inflation is accurately estimated. Between 2010 and 2014, the Producer Price Index (PPI) for microprocessors has seen a change in its rate of decline. From 2000 to 2009, the index fell on average 38.14 percent a year.¹ From 2010 to 2014, the index decreased only 4.21 percent a year. This change in index behavior has spurred interest in alternative methods that account for technological change in microprocessors.

The PPI measures only “pure” price change on the basis of market factors. It must exclude any price change or portion of a price change that is due to a change in the characteristics of a product. A change in the characteristics of a product is also called a quality change. The PPI must separate this pure price change from the quality change. For a product, such as a table, one can easily measure and account for the quality change from switching to oak from maple construction by removing the value of the switch from the price change. This procedure is known as quality adjustment. However, quality adjusting for microprocessor characteristics is more difficult because of their technological complexity. This challenge in properly accounting for the quality change has led to debate about whether the PPI for microprocessors is biased because it is not properly accounting for quality change.

This debate has guided our efforts to develop new quality-adjustment methods for microprocessors.² Some of the quality-adjustment methods proposed by other researchers have been helpful in guiding the general direction of our approach to quality adjustment, which we then refine and develop to suit the needs of the PPI for microprocessors. These methods involve using a type of statistical model for quality adjustment that has never been deployed in a PPI index before. In addition, we use statistical learning techniques in the development of our quality-adjustment method, which have never been used in an official price index before.³

In this article, we will (1) discuss the technical reasons for the debate over the possible magnitude of the bias of the PPI for microprocessors, (2) reexamine some of the results from a study claiming substantial bias in the microprocessors index, and (3) present a quality-adjustment method that both uses new methods and is developed with new methods.

The PPI for microprocessors is a matched-model index. Theoretically, a matched-model index tracks price changes from period to period for the same set of products. However, producers typically stop producing products after a certain amount of time and introduce new products with different characteristics; this scenario creates a problem of price comparison between different products. Before 2009, when new microprocessors were introduced, the prices of existing microprocessors would decline. In this case, a matched-model index would still capture price changes caused by factors such as technological improvements. The market is effectively valuing the technological change. After 2009, however, when new products were introduced, the prices of existing products would usually remain unchanged. This slower rate of decline could be interpreted as a slowdown of technological innovation in the semiconductor industry and as a signal for the end of Moore’s Law.

Moore’s Law states that the number of transistors on a chip doubles every 2 years, which is substantial because it has driven “feature-size reduction (scaling) that leads to better performance and cost reduction.”⁴ This combination of decreasing cost per transistor and increasing performance was responsible for the large declines in the microprocessors index before 2009.⁵ However, at very small feature sizes of microprocessors, which companies began to manufacture in the 2005–07 timeframe, power usage for a given area of a microprocessor began to increase.⁶ Increasing power usage per area makes increasing performance more difficult. While improvements in fabrication technology can address the challenge of increasing power usage per area, at least to some extent, it is clear that the feature-size reduction no longer delivers the same decreases in cost and increases in performance as it did previously.⁷

Although the slowdown of Moore’s Law is debatable, without question, microprocessors have changed substantially since 2009, from both a technological and pricing viewpoint.⁸ These changes have led to discussions about the PPI matched-model methodology for the microprocessors index and whether the index is showing a slower rate of quality increase than a hedonic approach would show. Researchers have used hedonic modeling methods to generate estimates of quality-adjusted price declines for computers.⁹ Since computers and microprocessors are both high-tech goods and share many similarities, the hedonic methods used for computers are readily applicable to microprocessors.

In a 2018 article, Byrne, Oliner, and Sichel, henceforth referred to as BOS, use a hedonic regression applied to microprocessors to construct a quality-adjusted index of price change for Intel desktop microprocessors.¹⁰ BOS examine a number of different model specifications that include both physical characteristics and performance benchmarks. Their preferred hedonic index shows a 42-percent price decline per year between 2009 and 2013.

Data and methods

To understand the 42-percent price change, we reconstruct the model presented in the BOS article.¹¹ We use Intel processors and prices to recreate a comparable dataset to do this analysis.¹² BOS uses a time-dummy hedonic model in their analysis of microprocessor prices. A time-dummy hedonic model uses a panel dataset to track price change over time. The BOS article uses 2 adjacent overlapping years for each of their panels. For instance, two of their panels are 2009–10 and 2010–11. Their preferred specification uses a time dummy and one other regressor, the log of a performance benchmark (SPEC speed [Standard Performance Evaluation Corporation speed]), with log price as the dependent variable.¹³ The coefficient on the time-dummy variable shows the price change between the two periods in the panel that is not explained by the other independent variables. The time-dummy coefficient can be used to calculate an annual inflation rate. The SPEC speed measures the performance of a microprocessor by calculating how long a microprocessor takes to run a suite of software. (See appendix A for more information on the SPEC benchmarks.)

In putting together their dataset, BOS identified two possible problems.¹⁴ The first possible problem is that Intel’s “posted prices do not represent true transactions prices because Intel offers progressively larger discounts to selected purchasers as models age.” The second possible problem is that Intel’s prices are unweighted, which “would put too much weight on price observations for which there were few transactions,” especially for older microprocessors. BOS contend that a newly introduced microprocessor will generate much more revenue than a microprocessor that is several years old, but an unweighted dataset will give them equal importance. Their solution for both of these possible problems was to “use the first four quarterly prices for each model (or fewer prices if the model is in the market for less than a year) and refer to this as the ‘early-price’ hedonic regression.”¹⁵ They aggregate these quarterly prices into yearly panels. For example, a microprocessor introduced in the third quarter of 2009 would have two observations for 2009 (third and fourth quarters) and two for 2010 (first and second quarters).

After recreating the BOS results, we explore the use of additional characteristics. The data we use in our following research are derived from Intel’s publicly available price sheets. Details on microprocessor characteristics were obtained from Intel’s ARK website.¹⁶ In addition to SPEC “speed” (and SPEC “rate,” which we discuss in the next section), we look at

·        cores—a hardware term that describes the number of independent central processing units (CPUs) on a single computing component (die or chip);

·        threads—a software term for the basic ordered sequence of instructions that can be passed through or processed by a single CPU core;

·        thermal design power (TDP)—the average power, in watts, that the microprocessor dissipates when operating at base frequency with all cores active under an Intel-defined high-complexity workload;

·        base frequency—the rate at which the microprocessor’s transistors open and close (The microprocessor base frequency is the operating point at which TDP is defined. Frequency is measured in gigahertz, or billion cycles per second.);

·        turbo frequency—the maximum single-core frequency at which the microprocessor is capable of operating using Intel Turbo Boost Technology;

·        cache—an area of fast memory located on the microprocessor (Intel’s Smart Cache refers to the architecture that allows all cores to dynamically share access to the last level cache); and

·        graphics—microprocessors that have an integrated graphics processing unit (GPU).¹⁷

All regressions in this article have log price as the dependent variable and include a time-dummy variable.

Criticisms of PPI microprocessors

The 42-percent decline per year in microprocessor inflation from the preferred BOS model is the result of using only a single regressor, the log of the SPEC speed performance benchmark. When additional characteristics are added to the regression, the rate of price decline becomes much smaller.

As already noted, BOS extensively examined regressions that included characteristics of microprocessors. Arguing that performance, as measured by benchmarks, is the most important aspect of a microprocessor, they focused on regressions that used only performance benchmarks.

PPI is interested in finding the best way to measure the value of the changes in microprocessors. We see nothing wrong in considering performance benchmarks to do this, but we believe that the regressions using these benchmarks must be able to at least approach the model evaluation criteria of other possible specifications, such as those that use characteristics. If regressions that use performance benchmarks exclusively cannot do this, then we cannot confidently use them for quality adjustment in the official PPI.

We replicated the BOS result using publicly available Intel data from 2009 to 2013 and applying their specification on early prices (mentioned earlier). We obtain an average annual price decline of 45.11 percent with an average adjusted R² of 0.6516. This result is comparable to the result obtained by BOS. It serves as a check on data compatibility and is shown in table 1.

The SPEC speed benchmark is designed to measure the speed of a core. According to Cisco,

This benchmark runs the integer or floating-point workloads end to end in a serial fashion, calculating a score based on the amount of time needed to complete the test. This test is meant to represent a single-threaded application or an application that is not designed to run in a multicore system.¹⁸

The SPEC rate benchmark is designed to measure the

throughput of a machine running simultaneous tasks over time. This benchmark runs several instances of the workloads at once and calculates a score based on how much work was done over a certain amount of time. This test represents a multithreaded application designed to run on a modern multicore system.¹⁹

The difference between the speed and rate tests can be illustrated by an example. Consider the three microprocessors (i3-6100, i7-4790K, and i7-5960X) in table 2, all with speed scores in the low- to mid-70s. As we can see, the SPEC speed benchmarks are similar for these three microprocessors, while the SPEC rate score better reflects the increase in performance with the increase in price from the i3-6100 to the i7-5960X. The disparity in rate scores is due mostly to different numbers of physical cores, which are two, four, and eight, respectively. The cache is another factor, increasing at even greater rate than the core count: 3, 8, and 20 megabytes. Intel, of course, charges for these features, as the large price spread illustrates. Running a regression with only the log of the SPEC rate benchmark drops the average annual price decline to 29.92 percent, with an average adjusted R² of 0.8356. This lower rate of price decline is because SPEC rate controls characteristics of microprocessors better than SPEC speed does. The results are shown in table 3.

However, there are reasons to not solely rely on SPEC benchmarks. SPEC has not registered the graphical improvements to many Intel desktop microprocessors in the last decade. In more recent years, Intel has been integrating a GPU onto their microprocessors. For this reason, a hedonic regression examining Intel CPUs should include controls for graphics. The performance of a GPU can be gauged by the number of execution units it has. The regressor we use for graphics is the log of the number of execution units; if it does not have an onboard GPU, we assign a zero.

Additional controls can also be added to distinguish microprocessors with equivalent benchmark performances but differing in operating frequencies, power consumption, thread counts, and cache. The nine-regressor model seen in table 4 includes log cores, log threads, log base frequency, log turbo frequency, log cache per core, log TDP, log graphical statistic, and the single and multicore SPEC benchmarks.

With the nine-regressor specification, the average annual price decline slips to 8.77 percent and the average adjusted R² rises to 0.9605. This rate of price decline is near the 12-percent to 14-percent declines BOS calculated with similar specifications.

We perform a standard F-test (where β = the coefficient on a variable and ε = the error term in an equation) on the two nested models, the restricted model with just the time dummy and SPEC speed and the unrestricted model, which include all our additional characteristics:

          log price = β₀ + β₁ Year Dummy + β₂ log Performance (“speed”) + ε

          log price = β₀ + β₁ Year Dummy + β₂ log Performance (“speed”) + β₃ log Performance (“rate”)

                         + β₄ log cores + β₅ log Threads + β₆ log Base Frequency + β₇ log Turbo Frequency
                         + β₈ log cache/cores + β₉ log TDP β₁₀ log + Graphics + ε

For every panel from 2009–10 through 2012–13, we test the null hypothesis (H₀) that our restricted parameters are equal to zero against the alternative hypothesis (H_A) that at least one parameter does not equal zero:

H₀: β₃ = β₄ = β₅ = β₆ = β₇ = β₈ = β₉ = β₁₀ = 0

H_A: at least one β ≠ 0

From the results of the equation (see text table), the null hypothesis is rejected in all the periods even at the 1-percent level. This result confirms our regression outputs in table 4, in which most of our additional characteristics are significant at the 5-percent level from 2009 to 2013.

F-statistic, 2009–13

Given the statistical significance of variables excluded by BOS, their model may be subject to omitted variable bias. The BOS estimate of inflation is not robust to changes in specification. Indeed, inflation varies greatly with specification changes. This finding raises the question of how different model specifications perform with respect to one another and with respect to the time-dummy coefficient that represents the annual price decline for microprocessors. To provide perspective on this question, we create every possible subset of the nine regressors, which gives 512 different linear regression specifications. We then take these 512 specifications and estimate them for all six of the 2-year panels. Finally, for every one of the 512 specifications, we calculate its average annual rate of inflation and average adjusted R² across the six 2-year panels. We get an average annual price decline of 14.35 percent. This rate of inflation is much lower than the model with only the log of SPEC speed as a regressor (the BOS specification), which has a 45.11-percent annual rate of decline, but it is greater than the official PPI for microprocessors, which had an annual rate of decline of 6.6 percent.

The bottom section of figure 1 arrays the 512 models by average adjusted R² and average annual price decline. Most cluster above the average adjusted R² of 0.6516 of the BOS specification. More important is the range of differences in average annual price declines relative to the BOS result, which appears to be an outlier. This divergent result is even more clearly seen in the top section histogram of figure 1. The blue dashed line shows the average price decline of 14.35 percent for all 512 models. The dotted red line shows the 45.11-percent price decline using the BOS specification, which is a larger rate of decline than that for every other possible model. This result lends evidence that the BOS specification does not include important variables and that it may be an outlier.

The annual deflation results obtained from our data are in line with the anecdotal evidence reported by industry observers. For instance, an article on the AnandTech website, detailing sixth-generation microprocessors, states that the increase was around 25 percent, in total, in performance between 2011 and 2015.²⁰

From our findings and the results of real-world performance testing from the AnandTech website, we find little empirical support that the 42-percent annual price decline from the preferred BOS model accurately represents the microprocessor industry between 2009 and 2013. However, the BOS criticism of the PPI microprocessors has sparked an evaluation of the PPI semiconductor index methodology and an examination of alternative quality-adjustment methods that PPI could implement.

Constructing a hedonic model for PPI microprocessors

PPI has studied quality-adjusting microprocessors in the past, most notably in an article by Michael Holdway, who looked at using hedonic quality adjustment for microprocessors.²¹ The article concluded that a hedonic model might be infeasible “if technology redefines characteristics over time” because “implicit prices for characteristics may be difficult to interpret.”²² The article then devised a method of valuing quality change using performance benchmarks. The main drawback of this method was that estimates of price change were sensitive to the choice of replacement microprocessors.

We find that the BOS article lays out a very useful framework for developing a hedonic model appropriate for use in the PPI. The BOS time-dummy approach solves some of the problems highlighted by the Holdway article because it does not require using the coefficients on the characteristics variables in the model or selecting replacement microprocessors. We believe the preferred BOS specification is not ideal for the needs of the PPI, and we explore methods for picking specifications that can include microprocessors characteristic variables.

Before we look at estimating a model for use in the PPI for microprocessors, we need to create a different dataset than the one BOS used. Because we are using a different dataset, note that any estimates of microprocessor price decline we calculated in this section are not comparable with estimates of price decline calculated in the previous section, in which we looked at the BOS model. We look at microprocessors from 2009 to 2017 and estimate models with overlapping two-period quarterly data. PPI indexes are published monthly, which means models need to be updated more often than annually. Since we are using quarterly data, we cannot use BOS early prices. Instead, we only include microprocessors introduced within a certain interval from a given quarter. In determining what that interval should be, looking at the reasoning behind the BOS early prices is helpful.

As stated earlier, BOS use early prices to address two possible problems. The first possible problem of posted prices not equaling transaction prices for older microprocessors has been examined by Kenneth Flamm.²³ For the retail microprocessors market, which is 20 percent of Intel’s microprocessors sales by volume, Flamm found “no evidence to support the suggestion that there was some structural change after 2006 in the relationship between observed Intel list price and observed retail market prices.”²⁴ Thus, at least some of Intel’s sales for older microprocessors are being accurately represented by its posted price list. BOS note, though, that the posted price list does not give any information on discounts off of the list price that Intel may be giving its largest customers, which make up most of its sales. However, we believe Flamm’s findings give us some flexibility on how long a reasonable interval we can set for including older microprocessors in our dataset.

The second problem that early prices address is that after a microprocessor is introduced, its sales peak and then decline. But important to remember is that Intel will continue to sell a microprocessor even after introducing a newer, more technologically advanced version of it is introduced. As mentioned earlier, the PPI tracks the entire production of companies, not just newly introduced products. Furthermore, when Intel introduces a microprocessor, shipments typically start off low and increase for several months before peaking.

For some microprocessors geared toward businesses, Intel guarantees that these microprocessors will be available and supported for 15 months.²⁵ If Intel is actively supporting a microprocessor, one can reasonably assume that it should still be selling at a substantial volume. For instance, when a business replaces employees’ computers, it usually does so over several months. This extended rollout means that the business will continue to purchase computers with the same microprocessor, even if newer microprocessors are introduced, in order to have a stable configuration. We use this 15-month interval when building our dataset. For example, for first quarter 2015, we include all microprocessors that were introduced from fourth quarter 2013 or later and that are still being sold in the first quarter 2015. This interval is similar to the first four quarterly prices that BOS used.

Several benchmarks are available for testing the performance of microprocessors. Some benchmarks specifically test the performance of rendering and encoding and others test the overall performance of a system. Instead of using the SPEC performance benchmarks, we use the PassMark CPU performance benchmark. (See appendix A for more information on PassMark.) We choose PassMark mainly because of the ease of obtaining the data from its website, which helps in the production nature of the PPI. PassMark also is a comprehensive benchmark that is able to capture the performance gain from multicore microprocessors, as table 5 shows.

In the first section of this article, we questioned the BOS model because it had a different inflation rate than most of the models with a much higher adjusted R². A first step in evaluating our quarterly data is reproducing figure 1 with them. Note that we constrain the log PassMark variable to be in every model we estimate with our quarterly data because we know for certain that microprocessor performance is increasing over time. We also think that the PassMark benchmark may be capable of accounting for improvements to microprocessors that are not associated with changes in any of the characteristics variables. Microprocessors are complex products with many attributes, so estimating a model that includes their every aspect is not possible. Since the PassMark benchmark shows total microprocessor performance, it may show quality improvements to microprocessors caused by changes to the characteristics we cannot include in our models.

The blue dashed line in figure 2 shows the average annual price decline of 12.74 percent. Just as we saw earlier, a wide variety of possible inflation rates exist. This finding presents us with the problem of selecting our preferred model.

While no definitive method of specification selection exists, the field of statistical learning offers techniques for objectively evaluating the performance of different model specifications. In the following excerpt, Hastie and colleagues give a basic overview behind statistical learning methods:

The generalization performance of a learning method relates to its prediction capability on independent test data. Assessment of this performance is extremely important in practice, since it guides the choice of learning method or model, and gives us a measure of quality of the ultimately chosen model.²⁶

It is important to emphasize that although statistical learning methods look at the predictive power of the model on the dependent variable, they are evaluating the overall quality of the model, including the model specification. We are using these methods to perform model selection by “estimating the performance of different models in order to choose the best one.”²⁷

Models that are overfitted can have a high adjusted R² while having poor out-of-sample predictive performance. One way to test for overfitting is to use a procedure known as validation. This validation involves splitting a dataset, estimating the model on one part of the dataset (the training set), and then predicting the dependent variable on the other part of the dataset (the validation set) with the use of the coefficients from the model estimated on the training set. The validation-set predictions of the dependent variable are then compared with the actual validation-set values of the dependent variable to give the prediction errors; the prediction errors are squared and then averaged, which gives the mean squared error (MSE). The lower the MSE is, the better the predictive performance of the model.

We use two different techniques to select model specifications. If we can estimate similar rates of inflation from specifications chosen using different techniques, this consistency would be a sign that we are selecting a reasonable model. With both techniques, we can pick different specifications for every panel. These techniques address Holdway’s criticism that because the characteristics of microprocessors change in their importance over time, a model with a fixed specification may become misspecified over time.²⁸

The first method we use is the Bayesian information criterion (BIC). Information criteria, in general, can be defined as “a goodness-of-fit term plus a penalty to control overfitting.”²⁹ BIC is a traditional technique for evaluating model specifications, but it can also be used for estimating the validation-set MSE of a model.³⁰ It does this by treating the entire dataset as the training set, and the goodness-of-fit measure calculated for the model estimated on the entire dataset is penalized in order to estimate what the MSE would be on a validation set. The main risk of using BIC for model selection is underfitting, which would be selecting fewer characteristics than the best model that can be supported by the data.³¹ Because many characteristics of microprocessors are correlated, there is a tendency for models with different numbers of characteristics to have similar measures of performance. When this happens, BIC tends to pick the model with the least number of characteristics. When we calculate the BIC for all possible models for every two-quarter overlapping panel and then select the model with the minimum BIC for every period, we get an average annual price decline of 10.69 percent between the first quarter 2009 and the third quarter 2017.

Tables 6 and 7 show the models chosen by the minimum BIC for each period (see appendixes B and C for additional information on the BIC and the MSE, respectively). The “Selected variables” in the tables do not include log PassMark or the time dummy since every model contains both of those variables.

Most of the selected models have at least four variables. There is also a decreasing rate of price decline, especially starting in 2011.

Using BIC to select a model specification has several advantages for the PPI. Because BIC is a widely known technique for model evaluation, it makes the process of model selection easy to explain to users of PPI data. These users will have more confidence and trust in our data when our methods are clear and transparent. Using BIC for model specification selection is also quick and easy to implement. This ease of implementation is important if a model will be used in the PPI. A PPI industry analyst would need to re-estimate the model quarterly. A hedonic model can only be used operationally in the PPI if the model can be developed efficiently.

The second model specification selection technique we use is k-fold cross-validation. Just as with validation, which we explained previously, this method objectively evaluates a model by assessing its out-of-sample predictive performance. The disadvantage of validation is that part of the dataset is not used to estimate the model, which increases the variability of the estimated model parameters. With k-fold cross-validation, the dataset is split into k parts. Each of the k parts is held out in turn (the validation set), and the model is estimated on the remaining data (the training set). Then, just as with validation, cross-validation calculates the MSE by making predictions on the validation set by using the model estimated on the training set. This procedure yields k MSEs, which are averaged to produce an overall MSE.

Performing k-fold cross-validation on every possible model is computationally intensive. To reduce the number of models to evaluate, we can first prescreen the dataset. It is important to note that the prescreening is only performed on the training set and not on the full dataset. With our dataset, we have seven possible regressors to choose from (the time dummy and log PassMark are always included). We start by calculating the residual sum of squares (RSS) for every model that contains just one regressor (plus the time dummy and log PassMark). The one-regressor model with the lowest RSS makes it through the prescreening. We then repeat this procedure for every model that contains two regressors (plus the time dummy and log PassMark). The two-regressor model with the lowest RSS makes it through the prescreening. We continue this process, increasing the number of regressors by one each time, until we have prescreened a model that contains six regressors (plus the time dummy and log PassMark). Because we have seven regressors, only one seven-regressor model exists. At the end of the prescreening procedure, we have seven models, which contain from one to seven regressors. We then use cross-validation to calculate the MSE for each of the seven models.³² (See appendix D for more details.) Since we use 10-fold cross-validation, we repeat this procedure 10 times.

Splitting the dataset into 10 folds is done randomly. To average the random variation from splitting the dataset, we perform the procedure just discussed 500 times and take the average MSE for each of the seven models.³³

Because we are performing this procedure 500 times (which means 5,000 different training sets), different specifications can possibly be selected for models of the same size during the prescreening procedure.³⁴ That is, at the end of the procedure, we know the MSE for models with from one to seven regressors, but we do not know which regressors are included in those models. To select the specific regressors, we find which number of regressors in the prescreening step had the lowest MSE and then find the RSS for every model with that number of regressors in the whole dataset. The model with the lowest RSS is then selected.

Only 16 of the 34 models had the same specifications selected by both methods. Despite this finding, the average annual price decline is very close across specifications, with the price change obtained from the cross-validation method declining 10.95 percent and the minimum BIC method declining 10.69 percent.

Displaying the results from the minimum BIC method and the minimum MSE method, table 8 summarizes the inflation rates and the corresponding indexes for the models chosen.

The two different methods of selecting specifications produce indexes that track closely over time. In figure 3, we compare the actual PPI for microprocessors with counterfactual hedonic indexes that adjust desktop microprocessor items with the inflation rates in the previous tables. Note that the PPI for microprocessors stopped publishing in March 2015 because it no longer met publication criteria.

The PPI microprocessors index fell, in total, 30.88 percent, whereas, at the same time, the minimum BIC model fell 38.97 percent and the minimum MSE model fell 39.09 percent. The PPI microprocessors index begins diverging substantially from the counterfactual indexes in the beginning of 2010. This result supports the hypothesis that after 2009, the matched-model methodology was no longer fully accounting for quality change for PPI microprocessors. The hedonic indexes are also very similar, which suggests that our hedonic estimates of price change are consistent, even when selected with the use of two different techniques. Most likely, if the notebook and server microprocessors were also adjusted with hedonic time-dummy models, the rate of decline for the hedonic indexes would be greater. This assumption is based on the inference that the time-dummy coefficients for the hypothetical notebook and server microprocessors models would be similar to the desktop models. Also important to note is that as an item declines in price, its relative revenue weight in an index declines, which lessens the items effect on the index over time.³⁵

In figure 4, we compare the semiconductors index for primary products (PPI code PCU334413334413P),³⁶ with counterfactual hedonic indexes that adjust desktop microprocessor items with the inflation rates in table 8. PPI semiconductors primary products has published for the entire time that we calculated the counterfactual indexes. PPI semiconductor primary products aggregates together indexes for different semiconductors products, including microprocessors.

The PPI semiconductors primary products index fell, in total, 29.37 percent while the minimum BIC model index and the minimum MSE model index both fell 30.92 percent. The hedonic indexes again show an overall greater decline than the PPI semiconductors primary products index, though it is minimal. This decline is the result of two factors. First, desktop microprocessors are a smaller share of PPI semiconductor primary products than they are of PPI microprocessors. Second, as an index declines, its relative weight also declines. As the PPI microprocessors index declines faster than other PPI semiconductor indexes, its relative weight in PPI semiconductor primary products declines.³⁷

Starting in January 2018, PPI began using the minimum MSE model to estimate prices for desktop microprocessor items in the official semiconductors index. The minimum MSE model was selected because statistical learning is a developing field, and we hope to refine our methods continually over time.

Conclusion

Challenges in recent years of continuing the historic trend of performance improvements of semiconductors have led to a debate about the rate of microprocessor price declines. Part of this debate, the BOS article, has a preferred model that has a very large rate of price decline in 2009–13. By estimating models with more characteristics, we have shown that the rate of price decline decreases and the goodness-of-fit measures for the models increase.

Drawing on past work done in hedonics, particularly the BOS article, we have devised an alternative to the matched-model methodology used for microprocessors in PPI semiconductors. Our models use overlapping adjacent quarters, a time dummy, and specifications selected with the statistical learning technique of repeated cross-validation. Our microprocessors models are the first time-dummy models used in the PPI and are the first to use a statistical learning technique in any official price index.

The counterfactual indexes we created using our models show that the official PPI for microprocessors was likely understating price declines, but not dramatically so. With the implementation of time-dummy models with a specification selected using statistical learning, the PPI may better represent the price movements of desktop microprocessors.

Acknowledgments

We first and foremost would like to thank Tim Erickson. He spent countless hours with us discussing economics, statistics, statistical learning, and the technical details of microprocessors. The knowledge we gained from these conversations made this article possible. We would also like to thank Kelly McConville, Deanna Bathgate, David Byrne, Stephen Oliner, Daniel Sichel, Ralph Bradley, Peter Uimonen, Brian Adams, and Vincent Russo for their assistance and comments.

Appendix A: SPEC and PassMark benchmarks

Our dataset includes the SPEC (Standard Performance Evaluation Corporation) central processing unit (CPU) 2006 benchmark score for desktop microprocessors.³⁸ We obtained SPEC benchmarks from the SPEC website in January 2016. Both SPEC speed and SPEC rate benchmarks were collected; the speed metrics are used for measuring the capability of a computer to complete a single task. The SPEC speed metric measures the performance of the system using a single core of the system microprocessor, which is greatly affected by the clock speed of the microprocessor and its cache size. The SPEC rate metric measures the throughput of a machine performing several simultaneous tasks. This metric provides a good overall measure of performance of modern multicore microprocessors. SPEC rate metrics are typically most affected by the number of microprocessor cores on a system. We include the SPEC rate benchmark to our evaluation because a key price-determining characteristic of today’s microprocessors is based on the number of cores it has.³⁹ The SPEC benchmark suite is used primarily by server and workstation manufacturers to performance test their products. Many low-end desktop CPUs do not have SPEC benchmark scores. To better reflect all the desktop CPUs that Intel produces, we turn to PassMark.

PassMark CPU benchmark results are gathered from users’ submissions to the PassMark website as well as from PassMark’s own internal testing. Its benchmarking software PerfomanceTest is available for purchase on the PassMark website. This software conducts eight different tests and then averages the results together to determine the CPUMark rating (a performance measure of the microprocessor) for a system. PassMark runs one simultaneous CPU test for every logical CPU, physical CPU core, or physical CPU package. The eight tests include an Integer Maths test, a Compression Test, a Prime Number Test, an Encryption Test, a Floating-Point Math Test, an Extended Instructions Test, a String Sorting test, and a Physics Test.⁴⁰

Appendix B: Selected quarterly models of minimum Bayesian information criterion

Appendix C: Selected quarterly models of minimum mean squared error

Appendix D: An introduction to statistical learning model specification selection

The basic steps that we use for prescreening and cross-validation come from An introduction to statistical learning:⁴¹

1.      Let M₀ denote the null model, which contains no (p) predictors. This model simply predicts the sample mean for each observation.

2.      For k = 1,2, . . . p:

a.      Fit all (p/k) models that contain k predictors.

b.      Pick the best among these (p/k) models, and call it M_k. Here, best is defined as having the smallest residual sum of squares, or equivalently R².

3. Select a single best model from among M₀, . . . , M_p using cross-validated prediction error, C_p (Akaike information criterion or AIC), Bayesian information criterion, or adjusted R².

For step 3, we only use cross-validation (10 fold). We repeat the steps 500 times, and we calculate the standard errors for each of the 1 through p models. The model with the smallest number of predictors whose standard error was within range of the lowest mean-squared-error value is selected.

The code we use to implement this technique is based on code from page 250 of An introduction to statistical learning.⁴² We added code to repeat the process 500 times and to calculate the standard errors.